Thin-film transistor (TFT) liquid crystal display (LCD) panels are known in the art. Typically, an LCD panel comprises an upper substrate, a lower substrate and a liquid crystal layer disposed between the upper and lower substrates, as shown in FIG. 1a. The upper substrate typically comprises a common electrode layer and a color filter layer. The lower substrate comprises a plurality of pixel electrodes to define the pixels of the LCD panel. In each pixel, the lower substrate comprises various electronic components such as one or more thin-film transistors (TFTs), one or more capacitors, at least one gate line, and at least one data line. FIG. 1b shows part of the lower substrate in a pixel and FIGS. 2A-2G illustrate the process steps of fabricating a TFT. As shown in FIG. 1b, a gate metal layer and a capacitor metal layer are separately deposited on a glass substrate, and a dielectric layer made of SiNx or the like is deposited over the metal layers (part of these layers are shown in FIGS. 2A and 2B). On the TFT, an amorphous silicon layer (a-Si:H) and a doped amorphous silicon layer (n+ a-Si:H) are deposited above the gate structure, as shown in FIG. 2C. A source/drain metal layer is deposited over the a-Si layers, as shown in FIG. 2D. A back-channel etching (BCE) step is used to define the source electrode and a drain electrode, as shown in FIG. 2E. A passivation layer made of SiNx or the like is deposited over the transistor structure, exposing a section of the drain electrode (FIG. 2F) so that the drain electrode can make electrical contact with a pixel electrode made of indium tin oxide (ITO), as shown in FIG. 2G. Apart from the TFT, the capacitor metal layer, the dielectric layer and the ITO layer form a storage capacitor for the pixel (see FIG. 1b). During one of the process steps, a metal layer is deposited on the dielectric layer to form a data line (see FIG. 1b).
This BCE process also removes part of the n+ a-Si:H and a-Si:H layers. If some of the n+ a-Si:H residues land between the gate or data line and pixel electrode (see FIG. 3), the pixel may become defective. FIG. 3 is a schematic representation showing a plan view of two adjacent pixels in an LCD panel. As shown in FIG. 3, a pixel is substantially defined by two adjacent gate lines and two adjacent data lines. A common line is typically provided in the middle of a row of pixels.
It is desirable and advantageous to provide a method to clear the n+ a-Si:H residues so as to improve the yield of LCD manufacturing.
Furthermore, when the ITO layer is deposited, some residues may also land between the gate or data line and the pixel electrode (see FIG. 6), and thus the pixel may also become defective. It is also desirable to provide a method to clear these ITO residues.